In attempting to use the area on printed wiring boards more efficiently, semiconductor chip manufacturers have recently been switching from larger, more cumbersome interconnection conventions, such as pin grid arrays ("PGAs") and the perimeter leaded quad flat packs ("QFPs"), to smaller conventions, such as ball grid arrays ("BGAs") and chip size packages ("CSPs"). Using BGA technology, semiconductor chips are typically interconnected to their supporting substrates using solder connections, such as with "flip-chip" technology. However, when solder alone is used to interconnect the chip contacts to the substrate, the columns of solder are generally designed to be short to maintain the solder's structural integrity. This results in significant elastic solder deformation during operation (thermal cycling) of the device which further results in increased susceptibility to solder cracking due to the mechanical stress of the differential coefficient of thermal expansion ("CTE") of the chip relative to the supporting substrate thereby reducing the reliability of the solder connection. In other words, when the chip heats up during use, both the chip and the substrate expand; and when the heat is removed, both the chip and the substrate contract. The problem that arises is that the chip and the substrate expand and contract at different rates and at different times, thereby stressing the interconnections between them. As the features of semiconductor chips continue to be reduced in size, the number of chips packed into a given area will be greater and the heat dissipated by the each of these chips will have a greater effect on the thermal mismatch problem. This further increases the need for a highly compliant interconnection scheme for the chips.
The solder cracking problem is exacerbated when more than one semiconductor chip is mounted in a package, such as in a multichip module. Multi-chip modules continue to grow in popularity; however, as more chips are packaged together, more heat will be dissipated by each package which, in turn, means the interconnections between a package and its supporting substrate will encounter greater mechanical stress due to thermal cycling. Further, as more chips are integrated into multichip modules, each package requires additional interconnections thereby increasing the overall rigidity of the connection between the module and its supporting substrate.
Still other prior art solutions make use of a underfill material disposed between the chip and the supporting substrate in an attempt to reduce the stress caused by CTE mismatch. Without the underfill material, this stress is typically concentrated at the weakest part of the solder balls. The underfill material allows this stress to be more uniformly spread out over the entire surface of the chip, supporting substrate and solder balls. Examples of the use of underfill materials may be found in U.S. Pat. Nos. 5,194,930, 5,203,076 and 5,249,101. All of these prior art solutions are aimed at reducing the shear stress endured by the interconnections caused by thermal cycling. However, each of these solutions also encounters significant problems such as insufficient compliancy and process cost.
U.S. Pat. Nos. 4,716,049 and 4,902,606 disclose a method for providing compressive pedestals in order to form spring-loaded connectors. However, the connectors made by the methods disclosed in these patents necessarily result in a pedestal having a rounded top which transition into legs that slope outwardly from the center/top of the pedestal. This limitation to the tops and legs substantially reduces the lateral (x-y) flexibility of the pedestal and the height of the pedestal in relation to its diameter at its base. Further, the thickness of the vacuum deposited metal legs is reduced significantly as the slope of the legs is increased such that they are substantially vertical or perpendicular to the chip surface. Thus, the pedestal disclosed in these patents is not satisfactory for use as a flexible connector where significant x-y compliance is required in the plane of the contacts.
U.S. Pat. Nos. 5,055,907 and 5,192,716 disclose structure and a method for producing a thin film multilayer wiring substrate having "reach-through" metallized vias designed to connect to chip contacts. These disclosed via connections are disclosed as being made of a metal which is different than the metal used in the wiring substrate so that the vias may be removed if rework is required. However, in many configurations, it is likely such solid metal vias or thin walled, hollow metal vias do not provide adequate CTE mismatch compensation during thermal cycling because the vias have no way to "flex" in response to the differential expansion rates of the attached structures.
Despite these and other efforts in the art, still further improvements in interconnection technology would be desirable.